FIG. 1 depicts a switch S1 utilized as a pass gate, allowing an input signal VIn appearing on an input terminal to pass through as an output signal VOut on an output terminal in response to a control signal VControl supplied to a control terminal. Switches can be implemented using transistors in a number of ways. FIG. 2 depicts an embodiment of a transistor realization 10 of the switch S1 depicted in FIG. 1. In FIG. 2, two PMOS transistors P1, P2 are arranged in series, with a first PMOS transistor P1 having a drain configured as the input terminal to receive the input signal VIn and having its source connected to the source of a second PMOS transistor P2, and a drain of the second PMOS transistor configured as the output terminal to deliver the output signal VOut. The gates of the PMOS transistors are connected together and configured as the control terminal to receive the control signal VControl that can turn the PMOS transistors P1, P2 on, and allow the input signal VIn to pass through to the output terminal, or turn the PMOS transistors P1, P2 off, and prevent the input signal VIn from passing through to the output terminal.
The PMOS transistors P1, P2 in FIG. 2 have their back gates connected to their sources. FIG. 3 depicts a cross-sectional view of an embodiment of a PMOS device 20. Other types of transistor cross-sections are also possible, however, including DMOS, LDMOS, and NMOS cross-sections, that are usable transistor switch embodiments, including in circuits discussed herein. The PMOS transistor 20 is formed on a p-type substrate (or substrate layer) 24, and includes an n-well 28 formed in the substrate 24, p-type source and drain regions 32, 36 formed in the n-well 28, and a gate 40, usually formed from polysilicon, separated from the n-well 28 by a dielectric layer 44. The n-well 28 is sometimes referred to as a back gate, as the voltage of the n-well 28 can affect the properties of a conduction channel formed in the n-well 28 during transistor operation. Often the back gate 28 is connected to the source 32, as is depicted in FIG. 3. One problem that results from such a connection, however, is that a body diode is formed between the drain 36 and the n-well 28 and, due to the connection of the source 32 to the back gate 28, the diode also effectively appears between the drain 36 and source 32, as depicted in FIG. 2 with dashed lines (D1, D2). One reason for arranging the PMOS transistors P1, P2 in series in the embodiment of FIG. 2 is to prevent the body diodes from conducting.
One problem with the switch embodiment 10 of FIG. 3 is the difficulty of delivering a proper control signal VControl to the control terminal. Merely delivering static on and off control signal voltages, having values relative to a supply voltage, to turn the PMOS transistors P1, P2 on or off does not result in optimal switch performance. During operation when the switch is turned on, as the input signal VIn varies and is passed to the output terminal from the input terminal, along the way it passes through the node connecting the sources of the two PMOS transistors P1, P2. The gate-to-source voltage of the PMOS transistors P1, P2 will thus vary if the gate voltage is static. The on-resistance of the PMOS transistors P1, P2, i.e., the resistance the PMOS transistors P1, P2 present from drain to source, however, is a function of their gate-to-source voltage. Therefore, a varying gate-to-source voltage will generate a varying on-resistance of the PMOS transistors P1, P2, which is an undesirable operational characteristic of the switch due to the resulting unpredictability and general degradation of switch performance metrics. Thus, there exists a need in the art for improved apparatuses and/or methods for providing and receiving signals to turn transistors on and off in transistor switch embodiments.